1. Field of the Invention
The present invention relates to a semiconductor device having a contact hole with a large aspect ratio, and more particularly to a semiconductor integrated circuit such as Dynamic Random Access Memory (DRAM) on gigabit level with high density surface interconnections, and a method of fabricating the same.
2. Description of the Related Art
In recent years, integration density of a semiconductor integrated circuit increases and particularly a high integration density on gigabit level is required in DRAM. Following such an increase of integration density of semiconductor integrated circuit, metallization techniques for making fine patterns of a surface interconnection and the contact holes for the surface interconnection are becoming indispensable. Among them, the metallization technique for connecting a semiconductor region such as a source/drain region formed on a semiconductor substrate to a conductor (metal interconnection) by opening a contact hole through an interlayer insulating film or the metallization technique for interconnection of multi-level wiring through a contact hole (via hole) and necessary metallization processes for these techniques are required to add many contrivances according to a decrease of the minimum feature size.
Problems in the conventional wiring techniques of DRAM will be described below. The case of connecting a bit line to a drain region of an access transistor is described here as an example of the conventional techniques. FIG. 1A is a top plan view illustrating a part of the memory cell of one-transistor (1-T) DRAM and shows a contact hole connected to a bit line 109-2 and other bit lines 109-1, 3. FIG. 1B is a cross-sectional view along the direction of I--I line in FIG. 1A, i.e. the direction of a bit line 109-2. FIG. 1C is a cross-sectional view along the direction perpendicular to II--II line in FIG. 1A, i.e. the direction of a bit line 109-2. An access transistor (nMOSFET) comprising an n.sup.+ drain region 106d, an n.sup.+ source region 106s and a polysilicon gate electrode 105 formed in a p-type silicon substrate 101 is shown. The gate 105 also serves as a word line. Though a storage capacitor connected to the n.sup.+ source region 106s is not shown in the figure, the n.sup.+ drain region 106d and the bit line 109-2 are connected each other through a contact plug 112.
A memory cell of the DRAM shown in FIGS. 1A-1C is manufactured by the following fabrication steps:
(a) First, an isolation region 102 is formed in a p-type silicon substrate 101 as shown in FIG. 2A. Next, a gate insulating film 103, a phosphor-doped polycrystalline silicon layer 105 and a silicon nitride (Si.sub.3 N.sub.4) layer 104 are deposited. Thereafter, the silicon nitride layer 104 and the polycrystalline silicon layer 105 are dry-etched using a photo-resist (hereafter denote simply as "resist") as an etching-mask and thus a polysilicon gate electrode 105 is formed.
(b) Next, a silicon oxide layer 107 and an n.sup.+ source and an n.sup.+ drain regions 106s and 106d, respectively of the nMOSFET are formed on the side wall of the polysilicon gate electrode 105 by ion implantation of for example, phosphor (.sup.31 P.sup.+) using the polysilicon gate electrode 105/silicon nitride layer 104 as an implantation mask and a thermal annealing after the ion implantation.
(c) Then, an interlayer insulating film 108 made from BPSG or another substance is deposited as shown in FIG. 2B, and the surface of the interlayer insulating film 108 is flattened to a predetermined thickness
(d) Next, the resist is patterned by photolithography technique as shown in FIGS. 2C and 2D. Then, grooves 109a, 109b and 109c for the formation of the bit lines are formed by etching using the resist as an etching mask. After etching, the resist is removed. FIG. 2D is a cross-sectional view corresponding to II-II direction in FIG. 1A.
(e) Next, as shown in FIG. 2E, a new resist 121 is patterned by photolithography. A connecting hole (contact hole) 110b is opened at a certain position by dry-etching using the resist 121 as an etching mask. After opening the contact hole, the resist is removed.
(f) Next, as shown in FIG. 2F, a barrier metal film 111, typically for example, Ti/TiN laminated film, is deposited. Thereafter, a tungsten film 112 is deposited and the surface of the tungsten film 112 is flattened by CMP (Chemical Mechanical Polishing). Then the bit lines of DRAM shown in FIGS. 1A-1C are brought to completion.
Thus, both the bit line and contact hole are filled up by the contact plug 112 composed of the barrier metal film 111 and tungsten film. Though the barrier metal film 111 is prepared to prevent silicon from mutual reaction with tungsten, such as a solid-state reaction called as "contact spiking", which leads to a leakage current, the step coverage is not so good because it is formed by sputtering.
The conventional semiconductor device and the fabricating method as above-mentioned generate the following problems:
(1) The aspect ratio for the contact hole 110b of the present DRAM is the order of 1.5 to 3 and further has a tendency to be required to have high values more than 4. When the contact hole 110b of DRAM is filled up by the tungsten plug 112, the tungsten film cannot be filled sufficiently into the interior of the contact hole 110b, if the aspect ratio of the contact hole 110b is high. This is due to the fact that the angle between the substrate surface and the side surface of the contact hole, .theta.6 (hereafter denote as "the taper angle"), is nearly a right angle. Consequently, it is hard to bury the tungsten plug 112 into the contact hole 110b uniformly.
(2) As shown in FIG. 3, even if the aspect ratio is reduced, the situation that the angle between the side surface of the contact hole 110a and the bottom surface of the bit line 109, .theta.7 (hereafter the corner having the angle .theta.7 is denoted as "shoulder"), is nearly a right angle (.theta.&gt;87.degree..about.89.degree.) cannot be improved, so that the barrier metal film 111 is hard to be deposited and there is a possibility of a penetration of tungsten plug 112 into silicon through a pinhole of the barrier metal film. That is, the barrier metal film 111 in the shoulder portion of the upper edge of contact hole becomes thick and by this increment of the thickness, the layer thickness at a corner "X" in the bottom surface is extremely reduced, resulting in possibly of a significant intermixing between tungsten plug 112 and silicon substrate 101 at the corner "X".
(3) In order to avoid the above-mentioned problem (2), a technique of increasing the hole diameter of the contact hole 110b only on the upper portion, keeping the diameter constant at the lower portion as shown in FIGS. 5(a) and (b), is proposed. However, in this case there is a possibility of short-circuiting with the neighboring bit line when the bit line spacing becomes narrow.
Namely, increasing the contact hole diameter only on the upper portion of the contact hole by isotropic etching as shown in FIG. 5(a) is examined. By this attempt, the above-mentioned barrier metal film 111 is nearly uniformly deposited, since the hole diameter on the upper portion of the above-mentioned contact hole 110b becomes large.
However, in this case a significant restriction on reducing the distance between the neighboring wiring grooves 109a and 109b is generated, because the hole diameters in the upper portions of the contact holes 110a and 110b come in contact with the neighboring wiring grooves 109b and 109a, respectively as shown in FIG. 5(b). Particularly, when the contact hole positions of the neighboring wirings approach, there is a possibility of direct interference between the contact holes and so, this restriction is further enlarged.